For high-power and high-frequency applications, the AlGaN/GaN heterostructure field-effect transistor (HFET) is regarded as an excellent candidate because of its high current density, high breakdown voltage and high saturation velocity performance.^[1,2] But, the large access region between the gate and the source/drain in the conventional lithography process will restrict the current and the operation frequency due to the increase of access resistance. Ion implantation is a method that can effectively reduce the access resistance. But this process is hard for industrial application because it is complicated and expensive.^[3] From a fabrication viewpoint, using the self-aligned-gate (SAG) process to suppress the access region can alleviate this problem.^[4] In a typical SAG process, a T-shaped gate is first fabricated and then used as a mask directly for ohmic metal evaporation. However, the fabrication of the SAG structure always encounters two problems. One is that the Schottky gate structure will degrade after annealing with source/drain electrodes since the annealing temperature is commonly higher than 800 °C,^[5] and the other is that the fabrication of T-shaped gate always needs multiple lithography or a multilayer photoresist.^[6] Therefore, it is relatively difficult and complex to realize a T-shaped gate with good morphology especially for AlGaN/GaN HFETs.

In this paper, we use the wet-etching method to fabricate the SAG AlGaN/GaN HFETs. The whole fabrication process for the T-shaped gate is simplified into two steps with just one-time lithography. Furthermore, a low-temperature ohmic process which only needs annealing below 600 °C is used to form the ohmic contact.^[7,8] Assisted with this process, the SAG AlGaN/GaN HFET is fabricated with good device performance. The thermal-stable titanium nitride (TiN) gate electrode shows no obvious degradation after low-temperature ohmic annealing.

TiN film with a thickness of 100 nm was deposited on sapphire substrate by reactive sputtering in Ar and N₂ mixture ambient with a Ti target.^[9] A 4-point method using a bridge structure with a length of 400 μm and a width of 15 μm was used to evaluate the wet-etching rate of TiN (inset in Fig. 1). From our previous study, solutions of BHF/HNO₃, NH₄OH, and H₂O₂ can be used to etch the TiN layer. Considering the ability to control the etching speed and the compatibility with the semiconductor technology, H₂O₂ is regarded as the most suitable etchant. A 30% H₂O₂ solution was heated to 95 °C to etch the TiN pattern. The 4-point method was used to measure the conductances of the patterned TiN film, after it had been etched for 0, 15, 35, 55, 75, and 85 s, respectively. The conductance of the TiN versus the etching time is shown in Fig. 1. The fitting result shows that the conductance decreases linearly with etching time with a slope of −2.31 mS/s and an intercept of 2.05 mS. In the etching process, even the TiN film can also be etched in the lateral direction, the width of the TiN bridge structure can be assumed to be a constant. Because even the etching depth in the lateral direction is equal to the TiN thickness, it only takes 1.32% of the 4-probe structure’s whole width. Assuming the etching rate α to be a constant, the conductance G with the etching time t can be described as a linear relationship as follows:

Fig. 1.

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	Fig. 1. Fitting result of the conductance against the etching time for the 4-point TiN pattern.

The epitaxial layers of the AlGaN/GaN HFET were grown by metal organic chemical vapor deposition (MOCVD) on a silicon substrate. It consisted of a buffer layer, a 1-μm i-GaN, a 25-nm i-AlGaN, and a 2-nm i-GaN from the bottom to the top. The Al mole fraction of the AlGaN layer was 25%. From the Hall measurement at room temperature, the mobility and average sheet resistance of the two-dimensional electron gas were about 2459 cm²·v^{− 1}·s^{− 1} and 385 Ω/☐, respectively.

The SAG HFETs were fabricated to test the feasibility of this method and to evaluate the device performance. Device fabrication was based on a standard photolithography technology. Mesa isolation with a thickness of 60 nm was first implemented by inductively coupled plasma (ICP) etching. Then, a 200-nm thick TiN layer was deposited on the whole surface of the wafer by the reactive sputtering process.^[10,11] A 3-μm-long gate footprint with a width of 55 μm was patterned using photolithography. Then a gate cap layer of Ti/Au (120 nm/120 nm) was deposited on the TiN surface. After the lift-off process, the left Ti/Au layer could act as an etching mask of the gate region. The whole sample was then dipped into a 30% H₂O₂ solution at 95 °C for 8 min, and a T-shaped gate was formed due to the isotropic property of the wet-etching method. What we need to mention is that the whole fabrication process of the T-shaped gate included only two steps and just one-time lithography. The source/drain region was treated by SiCl₄ plasma for 20 s with an ICP/bias power of 100 W/100 W, SiCl₄ flow of 3 sccm and treating pressure of 0.25 Pa, and then cleaned in BHF/HNO₃ (1:1) solution for 30 s to remove the possible Si contamination induced at the ICP treatment process.^[12] As ohmic metal, Al film with a thickness of 100 nm was then deposited and annealed in N₂ ambient at 575 °C for 1 min to form low temperature ohmic contact. Figure 2 shows the cross-sectional view of an SAG HFET.

Fig. 2.

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	Fig. 2. Cross-section view of the SAG HFET.

Based on the etching rate and the etching time of the SAG structure, the etching depth in our experiment could be calculated to be approximately 500 nm. Because the thickness of the TiN layer was approximately 200 nm, the lateral recess under the gate cap layer was assumed to be approximately 300 nm on each side due to the isotropic etching effect. A keystone shape TiN layer was assumed to have a top width of approximately 2 μm and the bottom width of approximately 2.4 μm. The width of the Ti/Au layer was designed to be 3 μm, so the width of the access region was approximately 0.3 μm on each side. Figure 3 shows the SEM images of the SAG HFET. From Fig. 3(b), it can be confirmed that the cap layer of the gate is 2.96 μm, which is consistent with the recommended value. However, it is difficult to take a cross-section view of the SEM photograph to confirm the size of the access region. Furthermore, there are some damages caused by the Al ball-up in the annealing process in the ohmic region (Fig. 3(a)), an Al/TiN structure can be utilized to solve this problem and will be used to fabricate the SAG HFETs in future.^[7] The ohmic contact was evaluated by the transmission line model (TLM) method.

Fig. 3.

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	Fig. 3. Typical low (a) and high (b) magnification SEM image of the SAG HFET.

Figure 4 shows the current–voltage (I–V) characteristics recorded on the TLM patterns with intervals of 5, 10, 15, 20, and 25 μm, respectively, and a width of 96 μm. The linear curves suggest that good ohmic contact behavior was formed between the metal stack and the semiconductor. An ohmic contact resistance of 0.32 Ω·mm and a sheet resistance of 399 Ω/☐ were calculated by the TLM method. In order to illustrate the advantage of the low temperature ohmic contact technology for SAG HFET, we fabricated some circular TiN Schottky diodes (with a diameter of around 150 μm) to evaluate the Schottky leak currents at different annealing temperatures. The I–V characteristics of the circular TiN Schottky diode are shown in Fig. 5(a). The gate leakage current without the annealing process was below 10^{− 5} A. While after being annealed at 575 °C and 850 °C for 1 min, the leakage currents increases to 10^{− 5} A and 10^{− 4} A, respectively. This result shows that the annealing process can damage the Schottky contact and increase the leak current, especially after being annealed at high temperature. Fortunately, the leakage current under being annealed at 575 °C is comparable to the sample without being annealed. The calculated ideality factor n and Schottky barrier height (SBH) of the TiN shottky diode under 575 °C annealing are 2.50 eV and 0.727 eV from the thermionic emission theory. The gate leakage of the bar-type SAG HFET as shown in Fig. 5(b) is only 10^{− 8} A, which confirms that the low temperature ohmic contact is useful for SAG HFET. In Fig. 6, the output and the transfer characteristics of the SAG HFETs are compared with a gate-first HFET, which was fabricated by the same low temperature ohmic process on the same wafer. The gate length and width of gate-first HFET were 2 μm and 55 μm respectively, and the access region size between gate and source/drain was 2 μm. For the gate-first HFET, a maximum current density and a transconductance were measured to be 500 mA/mm and 125 mS/mm respectively at a gate–source voltage of 1 V and a drain bias of 10 V. While for the SAG HFET, the maximum current density and the transconductance were measured to be approximately 750 mA/mm and 200 mS/mm respectively under the same condition. The increases of the drain current and the transconductance are ascribed to the decrease of access region from 2 μm to 0.3 μm in for the two devices.

Fig. 4.

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	Fig. 4. I–V characteristics and TLM fitting result of the TLM pattern.

Fig. 5.

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	Fig. 5. I–V characteristics of (a) the circular TiN Schottky diode and (b) the SAG HFET.

Fig. 6.

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	Fig. 6. Output (a) and transfer (b) characteristics of the SAG HFET and the gate-first HFET.

Generally, the gate length is required to be as small as possible for the high frequency application of the AlGaN/GaN HFET. Herein, we show that the wet-etching method as well as the low temperature ohmic contact technology is useful for SAG HFET fabrication. However, our result is just an evaluation method for the high frequency SAG HFET because of the gate length at the cap layer and the bottom of the T-shaped gate were 3 μm and 2 μm, respectively. Compared with our previous SAG HFET (with a gate length of approximately 500 nm) fabricated by electronic beam (EB) lithography, there still exists a large margin.^[6] In the future, we need to further combine these two technologies with the EB lithography to fabricate an SAG HFET with nanoscale size.

An SAG AlGaN/GaN HFET is fabricated based on wet-etching TiN gate and low-temperature ohmic process. Assisted by the ICP dry etching treatment, the ohmic contact resistance is only 0.32 Ω·mm. For the TiN gate structure, the gate leakage current is only 10^{− 8} A under the annealing process at 575 °C, confirming that the TiN gate is thermally reliable. An SAG HFET shows good electrical performance. The drain current density is more than 750 mA/mm and the transconductance is over 200 mS/mm under a drain bias of 10 V and gate–source voltage of 1 V, which are much higher than those of a gate-first HFET with the same gate length and width. Since the fabrication process is easy and the TiN Schottky gate is thermally stable, this method is suitable for improving the device performance.